1. Field of the Invention
The present invention relates to a nonvolatile memory cell, and more particularly, to a channel write/erase flash memory cell and its operation method.
2. Description of the Related Art
Please refer to FIG. 1. FIG. 1 is a cross-sectional view of a conventional flash memory cell 10. It includes a substrate 11, a first field oxide layer 12, a stacked gate 14, an N-type doping region 16, a shallow P-type doping region 18, a deep P-type doping region 20, and a source region 22.
The stacked gate 14 includes a control gate 13 and a floating gate 15 under the control gate 13. The N-type doping region 16 is formed between the first field oxide layer 12 and the stacked gate 14. The shallow P-type doping region 18 is formed next to the N-type doping region 16 and under the stacked gate 14. The deep P-type doping region 20 and the shallow P-type region 18 are doped with the same type of dopants. The deep P-type doping region 20 is formed under the N-type doping region 16 and is in contact with the first field oxide layer 12 and also the shallow P-type doping region 18. The deep P-type doping region 20 functions as a P well and its well depth is much deeper than the well depth of the shallow P-type doping region 18. The deep P-type doping region 20 and the N-type doping region 16 are electrically connected which functions as a drain terminal of the flash memory cell 10. The source region 22, functioning as a source terminal of the flash memory cell 10, is formed next to the shallow P-type region 18. Additionally, under the source region 22 a lightly doped region 24 is formed which is doped with the same type of dopants like the source region 22 but with a lighter density.
The programming method of the flash memory cell 10 will be explained below. When programming the flash memory cell 10, a word line voltage VWL=xe2x88x9210V is applied to the control gate 13, a bit line voltage VBL=5V is applied to the drain terminal, i.e. the shorted N-type doping region 16 and the deep P-type doping region 20, and no voltage is applied to the source terminal 22 so as to make it floating. Under this programming condition, electrons will eject from the floating gate 15 to the drain terminal due to the edge Fowler-Nordheim effect thereby achieving the effect of programming the flash memory cell 10.
However, in the above conventional programming method, a series of flash memory cells are programmed in a cell-by-cell sequence. As shown in FIG. 2, two flash memory cells 30 and 32 arranged in parallel are shown. Typically, it takes about 4 ms to complete the programming of one flash memory cell when a bit line voltage VBL=5V is applied to the flash memory cells 30 and 32. If 10 parallel flash memory cells are to be programmed, it will take 40 ms (10*4 ms) to complete the programming job. It means a great deal of time is needed when using the conventional programming method. Consequently, there is a need to provide a more effective flash memory structure and programming method.
Accordingly, it is the primary objective of the present invention to provide a new channel write/erase flash memory cell structure and also a new programming method.
In another aspect, the present invention provides a programming method in which a parasitic capacitor is used to temporally store bit line data to significantly increase the programming speed.
In one further aspect, the present invention provides a method of forming the aforementioned channel write/erase flash memory cell structure.
To achieve these and other advantages and in accordance with the purpose of the claimed invention, as embodied and broadly described herein, the present invention provides a channel write/erase flash memory cell structure capable of providing a pseudo-dynamic programming method. The structure includes a substrate of first conductivity type, a deep ion well of second conductivity type, an ion well of first conductivity type, a first oxide layer, a stacked gate, a doping region of first conductivity type, a shallow doping region of second conductivity type, and a deep doping region of second conductivity type.
The deep ion well of second conductivity type is formed in the substrate. The ion well of first conductivity type is positioned above the deep ion well of second conductivity type to create a parasitic capacitor during programming. The first oxide layer is formed on the substrate above the ion well of first conductivity type. The stacked gate is formed next to the first oxide layer and over the ion well of first conductivity type. The doping region of first conductivity type is positioned under the first oxide layer and on one side of the stacked gate to function as a drain. The shallow doping region of second conductivity type is formed next to the doping region of first conductivity type and under the stacked gate. The deep doping region of second conductivity type is positioned under the doping region of first conductivity type and is in contact with the shallow doping region of second conductivity type.
In the preferred embodiment of the present invention, the first conductivity type is N type and the second conductivity type is P type. The first oxide layer extends into the stacked gate with a decreasing oxide thickness for reducing interference during operation.
Further, a source doping region is formed next to the shallow doping region of second conductivity type and under the first oxide layer to function as a source terminal. The doping region of first conductivity type and the source doping region are doped with VA elements such as phosphorus. The shallow doping region of second conductivity type and the deep doping region of second conductivity type are both doped with IIIA elements such as boron.
Furthermore, the doping region of first conductivity type and the deep doping region of second conductivity type are short-circuited together by using, for example, a metal contact penetrating through the doping region of first conductivity type to the deep doping region of second conductivity type, or, alternatively, by using a metal contact formed across exposed doping region of first conductivity type and the deep doping region of second conductivity type.
Additionally, the present invention provides a method of forming a channel write/erase flash memory cell capable of performing a pseudo-dynamic programming method. The structure is formed by providing a substrate of first conductivity type, and then forming a deep ion well in the substrate. Next, an ion well of first conductivity type is formed in the deep ion well of second conductivity type. A first oxide layer is then formed over the ion well of first conductivity type. A stacked gate is formed later partially over the first oxide layer. A doping region of first conductivity type acting as a drain is formed under the first oxide layer and next to the stacked gate. A shallow doping region of second conductivity type is formed next to the doping region of first conductivity type and under the stacked gate. A deep doping region of second conductivity type is formed under the doping region of first conductivity type and is in contact with the shallow doping region of second conductivity type.
The method according to the present invention further includes a source doping region acting as a source terminal formed next to the shallow doping region of second conductivity type and under the first oxide layer. A metal contact is formed to short-circuit the doping region of first conductivity type and the deep doping region of second conductivity type. Or, a metal contact can be formed across the exposed doping region of first conductivity type and the deep doping region of second conductivity type so that these two regions can be short-circuited together. In one preferred embodiment according to the present invention, the substrate and the ion well of first conductivity type are both doped with N type dopants, and the deep ion well of second conductivity type is doped with P type dopants. To avoid interference during operation, the first oxide layer has a thickness that is thinner under the central part of the stacked gate and is thicker at two sides of the stacked gate.
Additionally, the present invention provides a pseudo-dynamic programming method for programming the channel write/erase flash memory cell. When programming, a word line voltage VWL, a source line voltage VSL, and a bit line voltage VBL are applied respectively to control gate, source terminal, and drain terminal of the flash memory cell. An N well, a deep P well and an N substrate are positioned in order under the flash memory cell. A well voltage VP is applied to the deep P well. The N well and the deep P well constitute a parasitic capacitor when programming the flash memory cell.
When performing an erase operation, the word line voltage VWL is in a high voltage level, the source line voltage VSL is in a voltage level relatively lower than the word line voltage VWL, and the bit line voltage VBL is floating. The well voltage VP and the source line voltage VSL are the same. When performing a programming operation, the word line voltage VWL is in a low voltage level, the bit line voltage VBL is in a voltage level relatively higher than the word line voltage VWL, and the source line voltage VSL is floating. The well voltage VP is in a voltage level higher than the word line voltage VWL but lower than the bit line voltage VBL.
When performing a read operation, the word line voltage VWL is in a high voltage level, the source line voltage VSL is in a voltage level relatively lower than the word line voltage VWL, and the bit line voltage VBL is in a voltage level relatively lower than the source line voltage VSL. The well voltage VP is in a voltage level lower than the source line voltage VSL.
It is to be understood that both the forgoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. Other advantages and features of the invention will be apparent from the following description, drawings and claims.